The present invention relates to electronic circuits that utilize phase-locked loop technology. In particular, the present invention relates to a method and apparatus for a phased-locked loop device that provides for enhanced jitter transfer characteristics.
Control systems can be categorized as open-loop or closed-loop systems. Open-loop control systems are often used in sequence control systems to guide a process through a sequence of predetermined steps. However, open-loop control systems do not yield high performance, due to errors between the input and output signals. These differences (xe2x80x9cerrorsxe2x80x9d) can result from disturbances acting on the system, variations of parameters in the system, and the like.
A closed-looped system, also termed a feedback control system, utilizes a feedback loop that allows the system to take corrective action in response to the xe2x80x9cerrorxe2x80x9d signal. Generally, closed-loop systems compare the amplitude of the input signal to that of the output signal with the result being the xe2x80x9cerrorxe2x80x9d signal. If the control system is functioning properly the xe2x80x9cerrorxe2x80x9d signal will ideally be zero.
In one electronic system, a closed-loop system may be employed to synchronize an internal clock signal with an external clock signal. In another electronic system, a closed-loop system may be employed to modulate and demodulate data transmission signals. In these types of electronic systems, a specific type of closed-loop system referred to as a phase-locked loop (PLL) is often employed.
A phase-locked loop (PLL) system generates an error signal by comparing the phase of the input signal to the phase of the output signal. The PLL is said to be xe2x80x9clockedxe2x80x9d when the phase difference (error signal) is within some minimum and maximum phase range. PLL systems are very useful in high noise environments.
Unwanted phase movement is known as xe2x80x9cJitterxe2x80x9d, and can be determined as the range of variation of the magnitude of the phase difference between the input signal and the output signal (the xe2x80x9cerror signalxe2x80x9d). Jitter peaking is the amount of overshoot in the error signal. A xe2x80x9ctransfer functionxe2x80x9d describes the input to output transfer characteristics of a PLL system and is similar to a low-pass filter response.
The present invention is directed to a method and apparatus for improving the response of a phase-locked loop (PLL) by reducing the jitter transfer characteristics. A new PLL system, referred to as an IS-PLL, includes an integrator and stability filter that are arranged to provide improved low frequency and high frequency performance while maintaining reduced jitter. The design of the IS-PLL is accomplished using superposition such that the integrator and stability filter designs are simplified. Design coefficients are chosen such that the system transfer function has a high frequency roll-off that is equivalent to a second order low-pass filter. Other design coefficients are chosen such that the system transfer function provides for improved DC tracking and reduced jitter. The present invention results in a third order system transfer function that can be realized with simplified design criteria.
In accordance with the invention, an apparatus for reducing jitter in a phase-locked loop that includes a phase detector circuit for producing an error signal in response to a phase difference between an input signal and a feedback signal is provided. A composite filter for producing a composite signal in response to the phase difference is also provided. The composite filter also includes an integrator and a stability filter. A gain circuit is provided that is arranged to produce an output signal in response to the composite signal. The output signal corresponds to a scaled version of the composite signal. An oscillator is provided for producing an oscillator signal in response to the output signal. The oscillator signal includes a corresponding phase that is employed as the feedback signal to the phase detector so that jitter in the output signal is reduced.
In accordance with an embodiment of the present invention, an IS-PLL includes a gain circuit, an integrator, and a stability filter. The IS-PLL has a system transfer function that is defined by three parameters (fK, fI, fS). The IS-PLL system has a filter parameter (fK) that corresponds to a product of each gain associated with the integrator, the stability filter, and the gain circuit. The filter parameter fS represents the stability filter, while another filter parameter fI represents the integrator. The ratio of fK/fI is in a range from about 32 to about 512. Also, the ratio of fS/fK is in a range from about 2 to about 5. The chosen parameters (fK, fI, fS) provide for reduced jitter peaking in the system transfer function. The system transfer function of the IS-PLL may be described as: H(s)=(sxc2x7fKxc2x7{fS+fI}+fKxc2x7fSxc2x7fI)/(S3+S2xc2x7fS+sxc2x7fK{fS+fI}+fKxc2x7fSxc2x7fI).
In another embodiment of the present invention, a method is directed to providing a phase-locked loop system that includes the functionality of the embodiments of the invention discussed above and below.